Semiconductor chips include a multiplicity of conductive layers, semiconductive layers, and/or insulative layers. These multiple layers are deposited by various means, and etched or otherwise processed to produce electrical devices, such as transistors, on the surface of the silicon wafer. For example, to form an intermetal dielectric (IMD) layer, a dielectric (insulative) layer is formed on top of a conductive layer. A second conductive layer is then formed upon the dielectric layer. The layers may then be further processed, for example by etching. It is critical that an IMD layer be free of voids or holes which could cause unwanted shorting between conductive layers.
The resolution of small mask images has become increasingly difficult due to light reflection and the thinning of resist layers over wafer topography. Small variations in the topography of a layer can be multiplied with the multiplication of layers. A number of techniques are used to offset the effects of a varied wafer topography. One widely used technique is the use of planarization layers, which act to fill in voids in the wafer topography, and to provide a smoothed wafer surface. For example, a spun-on-glass (SOG) layer can be used to provide a planarizing dielectric layer. In SOG processes, a glass such as silicon dioxide in a fast-evaporating solvent is deposited on a semiconductor wafer using spinning equipment such as that used for photoresist processes. After it is applied to the wafer, the glass film is baked, leaving a planarized silicon dioxide film.
SOG technology has limitations in VLSI processing. The glass as spun is brittle. Inorganic SOG films thicker than 0.2 .mu.m frequently crack during curing. Organic SOG films crack when exposed to oxygen plasma during resist-etching processes. It has therefore been desirable to provide a planarizing dielectric film by methods other than the traditional SOG methods.
CVD methods of producing a planarizing dielectric layer have been attempted, with some success. CVD-deposited silicon oxide films vary in structure and stoichiometry from thermally grown oxides. Depending on the deposition temperature, deposited oxides will have a lower density and different physical, chemical or mechanical properties, such as index of refraction, resistance to cracking, dielectric strength, and etch rate, when compared to thermally grown oxides. In many processes, the deposited film receives a high-temperature anneal in a process referred to as cure or densification. After the densification, the deposited silicon dioxide film is close to the structure and properties of a thermal oxide. However, high-temperature processing does not permit the use of underlying aluminum layers, which are adversely affected by temperatures above the melting point of aluminum (660.degree. C.).
In medium-temperature ranges, plasma enhanced chemical vapor deposition (PECVD) equipment has been used to generate an IMD layer. The oxide source is tetraethylorthosilicate [Si(OC.sub.2 H.sub.5).sub.4, TEOS]. TEOS is a type of silicon alkoxide that produces silicon dioxide through reaction with H.sub.2 O. Hatanaka et al. ("H.sub.2 O-TEOS Plasma CVD Realizing Dielectrics Having a Smooth Surface", VMIC Conference, p. 435-441, (IEEE, 1991), which is incorporated herein by reference in its entirety) have shown that a water-tetraethylorthosilicate oxide (H.sub.2 O-TEOS oxide) PECVD process, followed by a nitrogen anneal, can produce intermetal dielectric surfaces having planarization characteristics similar to spin- on-glass films, at moderate temperatures.
In order to provide a suitable surface for VLSI and ULSI devices, the IMD must be free of water, hydrogen, and residual hydrocarbons. However, the problem of charging effects due to water and residual hydrocarbons has been reported in PECVD TEOS oxide films that have high levels of water (H.sub.2 and/or O--H bonds) and hydrocarbon (C--H bond) concentrations. The H.sub.2 O-TEOS deposited/nitrogen anneal films of Hatanaka et al. demonstrate an unacceptably high level of water and hydrocarbon bonds when tested with infrared spectra after deposition.
Deposited silicon dioxide films are used as dielectric layers in multimetallization schemes, as insulation between polysilicon and metallization layers, as doping barriers, as diffusion sources, and as isolation regions. A common use of these layers is as a dielectric layer between two layers of conducting metal. The intermetal dielectric film must provide a gap-free planarization of submicron spaces.